This invention relates generally to semiconductor memory devices, and more particularly the invention relates to nitride read only memory (NROM) employing silicon-oxide-nitride-oxide-silicon (SONOS) structure for two bit and four bit data storage.
Memory is a key semiconductor electronic device in many electronic appliances such as PC computer, cellular phone, digital camera, networking, telecommunications, handheld mobile terminal markets and so on. There are mainly three kinds of semiconductor memory in the market: DRAM, SRAM and flash memory. Although DRAM still dominates the market, flash memory begins to play more and more important role in the market share.
Aggressive scaling of the semiconductor memory cells and the dramatic increase in the memory array size demand high density/low cost flash memory. Recently NROM SONOS (poly-silicon-oxide-nitride-oxide-silicon) memory device (FIG. 1) has attracted a lot of attention since it offers 2 bits/cell storage, which doubles the memory density per chip and reduces the cost per bit.
In programming the NROM cell, the word line (poly gate) and the N+ bit line 2 (BL2) are biased at 9V and 5V to program Bit 2, respectively. Hot electrons are injected into a local portion of the silicon nitride charge trap layer near the bit line 2 junction. During erasure of the Bit 2, the poly gate and BL2 are biased at −5V and 5V, respectively; the band-to-band tunneling induced hot holes near the BL2 junction are injected into the local portion of the silicon nitride charge trap layer to erase the stored electrons there. A reverse reading scheme is used to read the Bit 2: the poly gate and the bit line 1 (BL1) are biased in the normal reading mode to read the Bit 2, while the bit line 2 is grounded. A similar scheme is used to program/erase/read Bit 1.
In principle, the NROM memory is more scalable than the conventional floating gate flash memory. However, scaling the channel length of the NROM memory cell below 100 nm is very difficult. There are mainly two reasons: charge migration and charge injection control.
Assume in FIG. 1 that the channel length is 60 nm. After Bit 2 is programmed, the electrons are distributed over the channel region of 20 nm and the drain region of 20 nm near the bit line 2 junction. Hence the spacing between these two bits is 20 nm. Unfortunately, the electrons in Bit 2 will migrate towards the center of the channel during retention. If the electrons migrate for 20 nm, they will enter the Bit 1 charge trap location. Therefore it will be difficult to read Bit 1 from Bit 2. Very often, electrons can migrate for more than 20 nm during 10 years retention. Then, Bit 1 and Bit 2 will be mixed so finally there is only one Bit for each memory cell.
Further, since the nitride charge trap layer is continuous, it is difficult to control the electron injection location and the hole injection location during the program/erase cycle. Some electrons may not be completely erased if the hole injection location does not exactly overlap the electron injection location, which causes reliability problem. The lateral charge migration makes it worse, since some electrons already migrate to the center of the channel where there is no hole injection during the erase cycle.